Determining bias information for offsetting operating variations in memory cells

ABSTRACT

Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims the benefit of priority under 35 U.S.C.§120 as a continuation of U.S. patent application Ser. No. 13/776,590entitled “Determining Bias Information for Offsetting OperatingVariations in Memory Cells Based on Wordline Address,” filed on Feb. 25,2013, which claims the benefit of priority under 35 U.S.C. §119 as anonprovisional of U.S. Provisional Application No. 61/602,552, filedFeb. 23, 2012, the disclosures of which are hereby incorporated byreference in their entirety for all purposes.

TECHNICAL FIELD

The subject technology relates generally to memory devices and inparticular multi-level cell flash memory devices.

BACKGROUND

Flash memory bears little resemblance to a magnetic recording system.Commodity flash chips are closed systems with no external access toanalog signals, in sharp contrast to the typical Hard Disk Drive (HDD)where analog signals have always been available for detection. Eventhough the HDD is a complex electro-mechanical system and can suffercatastrophic failure, it has been possible to engineer drives to have alife expectancy with little to no degradation in performance, whichextend beyond their time of technical obsolescence. The data reliabilityof flash memory, on the other hand, is known to degrade through the lifecycle and therefore has a finite life. Consequently, when flash memorywas first conceived as a memory device the target error rate at theoutput of the chip has been kept very low, as opposed to systems wherestronger Error Correction Coding (ECC) may be used at the onset, likedeep space communications.

Lower priced Solid State Drives (SSD) are typically manufactured usingmulti-level cell (MLC) flash memory for increased data capacity, but MLChas less data reliability than single-level cell (SLC) flash memory.Consumer SSD manufacturers have mitigated such problems by employinginterleaving and/or providing excess capacity in conjunction withwear-leveling algorithms and/or limiting the amount of data the user canwrite to the device. MLC flash endurance, however, requiressophisticated algorithms to make them acceptable for enterprise SSDapplications where mission-critical data is stored.

SUMMARY

The subject technology provides a method for providing memory cell biasinformation for offsetting operation variations in memory cells.According to one aspect, a method may comprise programming a pluralityof cells within one or more memory blocks, determining one or moredistributions of cell program levels associated with a plurality ofwordlines in the selected memory blocks, determining a bias value for arespective one or more wordlines based on comparing one or more programlevels in a distribution of program levels associated with therespective one or more wordlines with one or more predeterminedprogramming levels, and storing the bias value in a parameter storagelocation associated with a memory controller of a solid state storagedevice, the parameter storage location configured to be accessible atruntime by the memory controller for retrieval of the bias value.

In another aspect, a machine-readable medium may comprisemachine-executable instructions thereon that, when executed by acomputer or machine, perform a method for providing memory cell biasinformation to a memory controller of a solid state drive. In thisregard, the method may comprise performing a predetermined number ofprogram/erase cycles on memory cells associated with a plurality ofidentical wordline addresses in a plurality of selected memory blocks,determining, for one or more of the wordline addresses, one or moredistributions of cell program levels associated with the predeterminednumber of program/erase cycles, generating a bias value for the one ormore of the wordline addresses based on comparing cell program levelsassociated with each of the one or more wordline addresses withpredetermined programming levels associated with a corresponding memorydie, and storing each bias value in a parameter storage locationassociated with the memory controller, the parameter storage locationconfigured to be accessible at runtime by the memory controller forretrieval of the bias values. In this regard, the method may furthercomprise repeating the steps of performing, determining, generating, andstoring for a plurality of predetermined program/erase cycle intervalsover an expected cycle lifetime of a memory block, each intervalcomprising a plurality of program/erase cycles.

In a further aspect, a method may include randomly selecting one or moregroups of memory cells from a plurality of selected memory die, each dieassociated with a common origin of manufacture, cycling the selectedgroups of memory cells for one or more cycle intervals, each cycleinterval comprising a predetermined number of program/erase cycles,determining, for each cycle interval, a shift in program levels formemory cells at one or more wordline addresses and resulting from thecycling, determining, for each cycle interval, a bias value foroffsetting the shift in program levels, and for restoring the programlevels to within a predetermine tolerance of a predetermined value forthe cycle interval, the predetermined value based on predetermined data,and storing each determined bias value in a parameter storage locationassociated with a memory controller of a solid state storage device, theparameter storage location configured to be accessible during storageoperations by the memory controller for retrieval of bias values basedon a wordline address and a current cycle interval.

It is understood that other configurations of the subject technologywill become readily apparent to those skilled in the art from thefollowing detailed description, wherein various configurations of thesubject technology are shown and described by way of illustration. Aswill be realized, the subject technology is capable of other anddifferent configurations and its several details are capable ofmodification in various other respects, all without departing from thescope of the subject technology. Accordingly, the drawings and detaileddescription are to be regarded as illustrative in nature and not asrestrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

A detailed description will be made with reference to the accompanyingdrawings:

FIG. 1 is a diagram illustrating an example graph diagram of fourpossible cell threshold voltage (V_(T)) distributions and complimentaryprogram verify levels for a group of memory cells in a multi-level cellflash memory storing two bits per cell.

FIG. 2 is a graph diagram illustrating an example threshold voltageevolution of a 2-bit MLC NAND flash memory cell with read levels andprogram verify levels chosen apriori at beginning of life.

FIGS. 3A and 3B depict actual measured variations in threshold voltagedistributions for different wordlines of an example memory block after50,000 program/erase cycles. FIG. 3A depicts the variations aftercycling, while FIG. 3B depicts the variations after cycling and bake.

FIG. 4 is a flowchart illustrating an example process for offsettingoperation variations in memory cells.

FIG. 5 depicts observed effects of wordline compensation on thresholdvoltage distributions in an example memory block corresponding to eachof six different wordlines along the flash block, with WL0 being thefirst wordline, WL63 being the last wordline, and others wordlines inbetween these two.

FIG. 6 is a flowchart illustrating an example process for adjustingoperating parameters in a storage device.

FIG. 7 depicts an example reduction in a number of errors for cells thathave been subject to wordline compensation measured on real MLC flash

FIG. 8 is a block diagram illustrating components of an example datastorage system.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description ofvarious configurations of the subject technology and is not intended torepresent the only configurations in which the subject technology may bepracticed. The appended drawings are incorporated herein and constitutea part of the detailed description. The detailed description includesspecific details for the purpose of providing a thorough understandingof the subject technology. However, the subject technology may bepracticed without these specific details. In some instances, structuresand components are shown in block diagram form in order to avoidobscuring the concepts of the subject technology. Like components arelabeled with identical element numbers for ease of understanding.

In a flash memory device, for example, with NAND architecture, memorycells are grouped in strings, with each string consisting of a set ofMOS transistors connected in series between a drain select transistor,connected to a bit line of the memory block, and a source selecttransistor, connected to a reference voltage distribution line. Eachmemory cell includes a floating-gate MOS transistor. When programming amemory cell, electrons are introduced into the floating-gate, by meansof Fowler-Nordheim (F-N) Tunneling. The non-volatility of the cell isdue to the electrons maintained within the floating-gate even when thedevice power supply is removed. Bits are stored by trapping charge onthe floating gate (an electrically isolated conductor) which stores alogic value defined by its threshold voltage (read threshold)commensurate with the electric charge stored. When the cell is erased,the electrons in the floating gate are pulled off by quantum tunneling(a tunnel current) from the floating gate to, for example, the sourceand/or substrate.

As a flash memory is cycled (that is, programmed and erased repeatedly),its physical qualities change. For example, the repeated placement andremoval of electrons on the floating gate during programming and eraseoperations, respectively, causes some excess electrons to be trapped inthe device. Also, when one or multiple cells are programmed, adjacentcells may experience an unexpected and undesired charge injection totheir floating gates, thus leading to corruption of data stored therein.For instance, electrons may leak into neighboring cells after prolongedstress due to the voltages at the gates of neighboring cells. Thethreshold voltages of these memory cells may eventually take values thatare different (higher or lower) than expected values, causing errorswhen the data is read. Generally, the damage done becomes a function ofthe field strength (voltage) and duration; that is, programming theflash memory to high threshold voltage conditions increases the rate ofdamage arising from both program and erase processes because it requireslonger duration and/or higher applied fields. For instance, addingenough electrons can change a cell from an erased state to a programmedstate.

In certain implementations, memory cells are arranged in an array ofcolumns (bitlines) and rows (wordlines). The address of a memory cellrepresents the intersection of a bitline and wordline corresponding tothe memory cell. Flash memory may further be composed of blocks, witheach block divided into pages. In MLC memory, every row of cells offlash composes 2 pages: a LSB and a MSB page. If a block has 128 pagesthen it has 64 rows of cells, with each row having two pages. Each rowbehaves differently because when cells are physically together in a diethey are subject to variations in voltages and resistances and the likeas part of the manufacturing process.

In NAND architecture, it has been found that the problem of degradationis especially problematic because each transistor in the string of thecells being read (e.g., at a bitline) receives an elevated voltagestress, even though only one cell of that string (e.g., at a location inthe bitline corresponding to a designated wordline) may be read at anyone time. Due to degradation, when programmed, the cells of some rows(wordlines) are further from their expected values (e.g., an expectedvoltage measured at a corresponding bitline) than others. It has beenobserved that these variations can be associated with individualwordlines. Accordingly, the subject technology characterizes thesevariations as a measurable value, and provides a mechanism to compensatefor the variations at runtime. For example, if cell voltages in awordline are found to shift (e.g., as a result of a characterizationprocess) then a bias may be introduced during the program or subsequentread operation to correct the programmed voltage or read value.Accordingly, the non-linearity of actual programming values betweencells in different wordlines is reduced, thereby reducing errors whenreading the cells.

Read retry capability has been introduced to perform data re-read withshifted voltage thresholds when read errors exceed error correctioncapability, however, read performances are further degraded by thenumber of read retries performed, as the host has to wait the time forthe subsequent reads to get the data. Endurance has been sacrificed tomeet the requirements of mainstream consumer flash application which arelow cost (maximum bits in each cell), long retention time (e.g.,extended dwell time), fast programming/erase, and low error rate to workwith unsophisticated data storage controllers. Contrary to industrypractice, the subject technology reduces the need for read retrycapability by providing, at runtime, memory cell bias information tomemory operations based on the location of the wordline and estimatedcycle age of the memory cell, thereby improving the reliability andendurance of the overall flash memory cell architecture, making theflash memory suitable for enterprise applications.

FIG. 1 is a diagram illustrating an example graph diagram of fourpossible cell threshold voltage (V_(T)) distributions and complimentaryprogram verify levels for a group of memory cells in a multi-level cellflash memory storing two bits per cell, according to one aspect of thesubject technology. The illustration shows the V_(T) distributions forflash with low cycles (“fresh”), distributions for word-out flash(“cycled”), and distributions for cycled flash which has gone throughhigh temperature exposure (“baked”). MLC NAND flash memory provides formore than one bit per cell by choosing between multiple levels ofelectrical charge (read level) to apply to the floating gates of itscells to achieve multiple states of conductivity, each occurring at adifferent voltage threshold V_(T). As depicted in FIG. 1, a MLC NANDcell is capable of storing four states (levels of charge) per cell,yielding two logical bits of information per cell: the Most SignificantBit (MSB) and Least Significant Bit (LSB). These two bits may make upcorresponding MSB and LSB pages of a memory block.

In some aspects, a NAND memory block is programmed one page at a timeusing an Incremental Step Programming Procedure (ISSP) and erased usinga similar Incremental Step Erase Procedure (ISEP). In some aspects, theISPP and/or ISEP may be performed by an internal flash controller (e.g.,within a flash memory) in response to one or more commands received froma data storage controller (e.g., a memory controller). For example, thememory cells that are to be programmed may be selected at the bit line.A “page operation” may be performed to apply a voltage at the gates ofeach cell in the memory page. A corresponding selection at the bit linescreates a voltage potential in the selected group of memory cells wherethe LSB is selected to be different (e.g., binary 10 or 00) than theerased L0 distribution state 201 (e.g., binary 11). Accordingly, ISPPincreases 202 the threshold voltage V_(T) 203 in the floating gates ofthe selected group of cells to create LSB distribution 204. Then, in asimilar manner, during a MSB page program operation, ISPP is applied tocreate an L1 distribution 205 from the erased L0 distribution 201 (e.g.,binary 01), or, an L2 distribution 206 (e.g., binary 00) or L3distribution 207 (e.g., binary 10) from the previously programmed LSBdistribution 204.

In some aspects, all of the above distributions are created from L0distribution 201 by applying a series of ISPP voltage pulses to thememory cells of the page which is being programmed. In some aspects, theISPP includes a series of voltage pulses that are applied in a steppattern with the amplitude of each pulse incrementally increased withincreasing pulse number, starting from a certain starting magnitude. Insome aspects, an internal flash controller of a flash memory may performa programming verification (sensing) operation in between each step.Alternatively, this verification operation may be performed after aspecific number of steps (the number of steps, for example, being storedon a storage medium). To verify a cell has been successfully programmed,the data storage controller applies a program verify voltage 208 in anattempt to conduct the cell. In some aspects, if the threshold voltageof a cell in the memory page is detected above a certain program verifylevel, the internal flash controller may stop further programming ofthat single cell by setting it to a program inhibit state.

In some aspects, LSB and MSB programming use different values of ISPPstarting magnitude and/or ISPP step magnitude. Accordingly, a differentISPP step and/or starting magnitudes can be used during the MSBprogramming of L1 distribution 205 than in the programming of L2distribution 206 and/or L3 distribution 207. This is because programmingto a higher V_(T) level requires the application of a higher voltagepotential between the MOS metal gate and the substrate. In some aspects,parameter values for a program operation may be stored in a storagemedium configured to be accessed by a data storage controller, and usedto determine (e.g., calculate) further values and/or issue commands tothe flash memory. The controller may be configured to communicate withthe flash memory via registers (e.g., the test register) and/or aninternal flash controller to provide commands for modifying certainparameters (e.g., nominal parameters set by the chip manufacturer) ofthe flash memory to vary the V_(T) distributions at run-time and/or tovary the voltages applied to conduct the memory cells (read levels). Aswill be further described, these parameters can be dynamicallydetermined and/or adjusted at run-time as a function of various circuitcharacteristics (e.g., program/erase cycle, retention time, BER,temperature) and/or in response to commands received from a host via ahost interface.

FIG. 2 is a graph diagram illustrating an example threshold voltageevolution of a 2-bit MLC NAND flash memory cell with read levels andprogram verify levels chosen apriori at beginning of life, according toone aspect of the subject technology. The topmost row represents thefour possible distributions of each programming state in a group ofmemory cells at a memory cell's beginning of life (BOL). The respectiveprogramming distributions of L0 distribution 201, L1 distribution 205,L2 distribution 206, and L3 distribution 207 are shown along a voltagethreshold continuum 301. The middle row of FIG. 2 depicts an exemplaryprogression of the programming distributions after repeatedprogram/erase cycling. The buildup of electrons trapped on the floatinggates of the memory cells has caused some cells to be programmed withhigher voltage thresholds (increasing the standard deviation of thedistribution at a higher V_(T)). This shift 306 in voltage thresholdsmay eventually cause the right edges of the V_(T) distributions to reachthe higher adjacent read levels. When the V_(T) of some of the cells inthe distributions begin to cross 307 the higher read levels, thelikelihood that a read operation will produce an error increases. Thebottom row depicts an exemplary result of an extended retention time(e.g., dwell time) on the memory cells. As the number of program/erasecycles increases, some of the memory cells lose electrons, causing theirvoltage thresholds to drop (increasing the standard deviation of thedeviation at lower V_(T)). This V_(T) drop is a function of both theamount of cycling and the temperature the cell has been subjected to.This shift 308 may eventually cause the left edges of the V_(T)distributions to reach the lower adjacent read levels. The more cyclesover which data is retained, and the higher the temperature, the moreextreme the decline. If the read levels remain fixed, the V_(T)distributions that have crossed 309 the next lower read level may causesignificant errors.

With reference to the top row of FIG. 2, after ISPP, the edges of eachof the distributions are suitably spaced from adjacent read levels. Insome aspects, spacing can be altered by setting program verify voltages305 (e.g., PV1, PV2, and/or PV3) during the verification operationsufficiently higher than a lower read level, but sufficiently low enoughto prevent even those cells in the distribution having the highest V_(T)(largest deviation) from crossing the next higher voltage correspondingto the read level. To ensure that all cells in a distribution willconduct, a read level voltage greater than the distribution is applied.In this regard, RL1 voltage 302 will cause cells in L0 distribution 201to conduct. RL2 voltage 303 will cause cells in L1 distribution 205 toconduct, RL3 voltage 304 will cause cells in L2 distribution to conduct,and so on. Where, as depicted by FIG. 2, only four states are available,RL3 voltage 304 will not cause any cells in L3 distribution 207 toconduct. Generally, for N distributions there will be N−1 read levels.In the depicted example, there are four distributions (of states) andthree read levels. Those skilled in the art will recognize that theremay be eight, sixteen, or more distributions without departing from thescope of the subject technology.

FIG. 3A depicts observed variations in threshold voltage distributionsfor different wordlines in an example memory block after 50,000program/erase cycles, for one particular flash supplier. FIG. 3B showsthe same observation for another flash supplier. Flash memory thresholdvoltage distributions are seen to vary depending on the wordlineaddress. Current flash operations may be performed with program verifyand read level values independent from wordline address and produce anundesirable high number of bits in error where read level placement isnot optimal. The subject technology, however, compensates for wordlinemisalignment by either modifying program verify levels at program timeor modifying read levels at read time based on wordline address. Thesemodifications may vary depending of the number of program/erase cyclesexperienced by the flash memory.

As will be described in further detail, an adjusted program verify level305 may be generated based on cycle information and/or a wordlineaddress of cells being programmed. For example, a data storagecontroller may monitor program/erase cycles and, for a programoperation, adjust the program verify level based on a bias valuecorresponding to a predetermined number of cycles. In another example,the adjustment may be based on retention time (e.g., dwell time) after acertain number of cycles.

A storage system maintains one or more lookup tables (e.g., on a storagemedium) for storing values pertaining to program verify levels 305.Additionally or in the alternative, the one or more lookup tables maystore a program verify level bias adjustment to be applied to cells atdesignated wordline addresses so that cells in each wordline may beadjusted differently than other wordlines. The bias values may beindexed by wordline address (or page or block address) and memory cyclecondition (e.g., a number or range of program/erase cycles, retentiontime, bit error rate (BER), or die temperature of a flash memory). Thedata storage controller may index the lookup table by the wordlineaddress and cycle condition to retrieve a bias value for adjusting theprogram verify level. As the condition(s) related to a flash memorychange over time, the data storage controller may index the lookup tableto determine the correct bias value to use for the changed condition(s).The controller then verifies programming levels using the adjustedprogram verify level. In some aspects, the controller may apply the biasvalue to generate a program verify level and then provide the programverify level to the flash memory by setting values of registers (e.g.,the test register), and/or by sending one or more commands to aninternal flash controller of the flash memory. In other aspects, thecontroller may bias program verify level at beginning of life (BOL) to ahigher value, for example, than the default value provided by the flashmanufacturer, in anticipation of extended cycles or retention times. Infurther aspects, the controller may determine a lower program verifylevel to reduce BER (e.g., due to excessive cycling).

The controller may also be configured to adjust read levels (e.g., readlevel 303) to higher or lower values to reduce BER and extend theendurance of the flash memory. Similar to the procedure describedpreviously with regard to program verify levels, read levels may also bebased on dynamically changing memory cycle conditions. As thecondition(s) related to the flash memory change over time, thecontroller may index one or more lookup tables to determine a bias foradjusting a read level according to the changed condition(s). Asdescribed previously with regard to program verify levels, the one ormore lookup tables may store a single read level adjustment to beapplied to cells in a specific wordline so that the wordline may beadjusted differently than other wordlines.

The previously described lookup tables (e.g., for program voltage levelsand/or read levels) may be initially populated based on acharacterization of the flash memory die (e.g., based on data collectedfrom a simulation of the flash memory, or test data received fromtesting a memory die). The amount by which the read levels can beadjusted may vary depending on the memory chip specifications and/orother qualities set by the manufacturer and the subject technology isnot limited to any particular value or values. For example, the flashmemory may be cycled to a specific number of cycles (e.g., 20,000program/erase cycles) and values for read levels and/or program verifylevels for each distribution (e.g., L1, L2, and L3) compared tomanufacturer values. Bias values may then be determined for eachwordline address based on the comparison between the cycled value andmanufacturer data.

Once the bias values are determined, they are stored in the one or morelookup tables to be indexed by wordline address and memory cyclecondition (e.g., cycle count). The process may then be repeated toselect values at successive cycle intervals (e.g., “BOL”, “low cycles”,“mid cycles”, “EOL”). Accordingly, to improve bit error rate, a biasvalue as a function of wear (cycles) may be established for futureapplication in a memory operation when the flash memory reaches a cyclecount corresponding to a respective cycle interval.

To reduce the number of index entries, wordlines having similar biasvalues (e.g., adjacent wordlines) may be grouped together. A bias valuefor a group wordlines may be a value selected to be within apredetermined deviation of bias values determined (or observed) for eachof the group of wordlines. The bias value may be a value determined forone of the wordlines in the group. In one example, WL0 through WL15 mayshare the same bias, WL16 through WL31 may share the same bias, and thelike. These groups of bias values may be used in either programming orread operations.

A combination of read levels and program verify levels generating thelowest BER may be found for each wordline address at each adjustmentperiod (number of cycles or length of retention time). In some aspects,the adjustment period (e.g., range of cycles) may be at least partiallydetermined by a predetermined maximum acceptable BER. The maximumacceptable BER may be determined by a maximum number of bits correctableby ECC. The number of bit errors is proportional to the number of cellvoltage “transitions” that occur when an edge of a V_(T) distributioncrosses an adjacent read level (e.g., FIG. 2, bottom row). In someaspects, the adjustment can be made to minimize transitions within thecapability of ECC. In view of this disclosure, those skilled in the artwill recognize how to simulate and/or test flash memory in order toselect adjusted read levels and/or program verify levels (at each levelof cell distribution) for placement in their respective one or morelookup tables.

FIG. 4 is a flowchart illustrating an example process for offsettingoperation variations in memory cells, according to one aspect of thesubject technology. According to some aspects, one or more blocks ofFIG. 4 may be executed by a computing system (including, e.g., a datastorage controller of an SSD, processor, or the like). Similarly, anon-transitory machine-readable medium may include machine-executableinstructions thereon that, when executed by a computer or machine,perform the blocks of FIG. 4. Accordingly, the blocks of FIG. 4 may beperformed within the context of a manufacturing or engineering testingenvironment.

In block 401, one or more memory die are selected from a group of memorydie. In some aspects, the group of memory die is associated with acommon origin of manufacture. For example, the group of memory die maybe selected from a lot associated with the same manufacturing date ormanufacturing process. A designated lot of memory die may be receivedfrom a given manufacturer, and the one or more selected memory die arerandomly selected from the lot. The one or more memory die may bemanually selected, or automatically selected by a computing algorithmfor selecting memory die.

In block 402, one or more memory blocks are selected from within theselected memory die. For the purpose of this disclosure a “memory block”may also be a “page” of memory, or other similarly situated memory cellsorganized as a group. The one or more memory blocks may be randomlyselected by address, or manually selected by identifying one or morepredetermined addresses.

In block 403, the system programs a group of cells within the selectedmemory blocks. In some aspects, the group of cells may be erased andreprogrammed for a predetermined number of times (e.g., 10,000program/erase cycles). For example, a number of program/erase cycleintervals may be selected, each interval being separated by a number ofprogram/erase cycles such that the intervals substantially span anexpected lifetime of the solid state drive. If the expected cyclelifetime of the solid state drive is 100 k program/erase cycles then theselected intervals may be located at 1,000, 20,000, 40,000, 75,000, and100,000 program/erase cycles. Other intervals may be selected. Forexample, each interval may be separated by a similar number of cycles,for example, each 10,000, 20,000, or 25,000 program/erase cycles.

The program/erase cycles may be performed on cells associated with agroup of identical wordlines in the selected memory blocks over thenumber of program/erase cycle intervals. For example, the program/erasecycles may be performed on a select number of wordline addresses acrossthe selected blocks and/or memory die. In this regard, cells at theidentical memory addresses of each block in the group of selected blocksmay be subjected to the same number of program/erase cycles.

In block 404, the system determines one or more distributions of cellprogram levels associated with a group of wordlines in the selectedmemory blocks. For example, a distribution may be associated with awordline by being associated with an address of the wordline.Accordingly, a distribution may be for cells in the group of selectedblocks at the same wordline address. Additionally or in the alternative,the distribution of the cells may be determined for each interval. Forexample, the program levels for cells in the distribution may bedetermined for cells at the same wordline address and/or bitline addressacross all of the selected blocks.

In block 405, a bias value for a respective wordline is generated basedon comparing one or more program levels in a distribution of programlevels associated with the respective wordline with one or morepredetermined programming levels (e.g., determined from manufacturingdata associated with a corresponding memory die). The bias value, whenapplied to a program (or read) operation, offsets a shift in programlevels, and may restore the program levels to within a predeterminetolerance of a predetermined value for the cycle interval, thepredetermined value based on the predetermined programming levels. Thepredetermined programming levels, for example, may contain expectedvalues for cells at an address after a number of program/erase cyclesbased on previously conducted simulation results, or derived fromspecifications provided by the manufacturer of the corresponding memorydie.

The bias value for a respective wordline may represent a shift in aminimum or maximum program level associated with a distribution of cellprogram levels associated with the wordline (e.g., at a wordlineaddress) from an expected minimum or maximum cell program level based onthe predetermined programming levels. Additionally or in thealternative, the bias value for a respective wordline may represent anaverage shift in a distribution of cell program levels associated withthe wordline from expected cell program levels based on thepredetermined programming levels.

In block 406, the bias value is stored in a parameter storage location(e.g., a lookup table) associated with a data storage controller of asolid state storage device, the parameter storage location configured tobe accessible at runtime by the data storage controller for retrieval ofthe bias value. Accordingly, the parameter storage location may beconfigured to provide the bias value to the data storage controllerduring a memory operation based on a provided wordline address and acurrent program/erase interval. In this regard, multiple bias values mayexist for different program/erase cycle intervals for a given memoryaddress.

In some aspects, the memory operation may include a program operation ora read operation. The data storage controller may utilize one or moreparameters during the memory operation depending on the type ofoperation. For example, where the memory operation is a read operation,the data storage controller may set a program read level (e.g., avoltage level placed at the bitline to activate the memory cell). Wherethe memory operation is a program operation the data storage controllermay set a program verify level. Additionally or in the alternative, theprogram verify level may be set within the flash memory. For example,the data storage controller may be configured to program the flashmemory (e.g., via one or more registers of the flash memory) with aprogram verify level to use for a certain range of memory cycleconditions (e.g., program/erase cycles), and/or adjust the programverify level of the flash memory on a current memory cycle conditionsatisfying a predetermined threshold (e.g., greater than a number ofcycles, or within a new cycle range).

If the bias value represents a shift in program levels after a number ofprogram/erase cycles, the bias value may be applied to either the verifylevel or read level to correct wordline misalignment over the lifetimeof the memory. If the data storage controller is going to correctwordline misalignment at read time then the bias will be applied toadjust the read level in accordance with the interval corresponding tothe current program/erase cycle. In this case, the bias may be added toa default read level used by the data storage controller and/or theflash memory device. If the data storage controller is going to correctwordline misalignment at program time then the bias may be applied toadjust the program verify level in accordance with the intervalcorresponding to the current program/erase cycle. In some aspects, apolarity of the bias value may be reversed before the bias value isstored. For example, program verify levels may require subtraction ofthe bias from a default value. To reduce overhead during the programoperation, the bias value stored in the parameter storage location maybe the negative of the shift determined in block 405.

Compensating for wordline misalignment at program time by modifyingprogram verify levels provides a significant improvement to the readlevel margins with fixed read level. Additionally, changing the readlevel as function of wordline address before performing read operationsmay be used to correct residual misalignment from compensation atprogram time and to account for distribution misalignment betweenwordlines that develops after program time. Compensation of the readlevel (or verify level) can be applied on a per-wordline basis or to agroup of wordlines within a block. The modification values to either theprogram verify levels or the read levels may be determined based onexperimental data or by simulation data.

FIG. 5 depicts observed effects of wordline compensation on thresholdvoltage distributions in an example memory block corresponding to eachof six different wordlines, according to one aspect of the subjecttechnology. As compared to FIG. 3A, the threshold voltage distributionsare seen as more aligned with each other and their expected values.

FIG. 6 is a flowchart illustrating an example process for adjustingoperating parameters in a storage device, according to one aspect of thesubject technology. According to some aspects, one or more blocks ofFIG. 6 may be executed by a solid state storage device, including, forexample, a data storage controller. Similarly, a non-transitorymachine-readable medium associated with the data storage controller mayinclude machine-executable instructions thereon that, when executed by acomputer or machine, perform the blocks of FIG. 6. This wordlineprogramming compensation may result in a reduced number of bits in errorcompared to not using the compensation technique.

In block 601, a memory cycle condition associated with a block of memorycells is determined in connection with a memory operation to beperformed on the block of memory cells. For example, the memory cyclecondition may be a current number of program/erase cycles. The datastorage controller may store information about each block, including thenumber of program/erase cycles already performed on a block. The datastorage controller may then check the stored information prior toperforming the memory operation (e.g., prior to performing a program orread operation on the block). In another example, the memory cyclecondition may be a data retention time associated with the block ofmemory cells.

In block 602, the memory cycle condition is checked to determine whetherit satisfies a predetermined threshold. The memory cycle condition mayinclude, for example, a current number of program/erase cyclesassociated with the block of memory cells, and the predeterminedthreshold may include a predetermined number of program/erase cycles, orrange of cycles. If the memory cycle condition does not satisfy thepredetermined threshold (e.g., the current number of program/erasecycles for the block are not within a predetermined range of cycles)then the process returns to block 601 for the next operation.

On the memory cycle condition satisfying the predetermined threshold(e.g., the current number of program % erase cycles for the block iswithin a predetermined range or greater than a predetermined number ofcycles), in block 603, the storage device retrieves, from the parameterstorage location, one or more stored bias values for the memoryoperation based on one or more wordlines associated with the memoryoperation. In this regard, a data storage controller associated with thestorage device may be in the process of undertaking a programming orreading of cells at one or more memory addresses. Accordingly, the oneor more wordlines will be wordlines corresponding to the memoryaddresses.

The one or more stored bias values offset a current shift in cellprogram levels associated with the one or more wordlines, and, whenapplied to the memory operation, restore the cell program levels towithin a predetermine tolerance of a predetermined value for the currentmemory cycle condition. In this regard, the predetermined value for thecurrent memory cycle condition may include a minimum or maximum cellprogram level based on predetermined programming levels for adistribution of cell program levels.

In block 604, one or more parameters of the memory operation areadjusted based on the one or more stored bias values. If the memoryoperation is a read operation then the one or more parameters mayinclude a read level. If the memory operation is a program operationthen the one or more parameters may include a program verify level. Asdescribed previously, the data storage controller may be configured toprogram the flash memory (e.g., via one or more registers of the flashmemory) with a program verify level to use for a certain range of memorycycle conditions (e.g., a range of program/erase cycles), and/or adjustthe program verify level of the flash memory on a current memory cyclecondition satisfying a predetermined threshold (e.g., greater than anumber of cycles, or within a new cycle range). After the one or moreparameters are adjusted, in block 605, the memory operation is performedon the block of memory cells using the adjusted parameters.

As described previously with respect to the characterization procedureof FIG. 4, only a selected number of blocks may have been characterizedto generate bias values. In some aspects, the previously generated biasvalues may be sufficient for all blocks in a flash memory or for allflash memory in a solid state drive. The lookup table may be configuredto store a bias value to be used with all memory blocks, or may storebias values for each block of memory. The lookup table may, for example,include a storage location for each block of memory (e.g., whether ornot that block was previously characterized), which is preloaded with anidentical bias values that were determined as part of thecharacterization.

The data storage controller may be configured to dynamically adjust biasvalues for use in the blocks as it learns new information about theblocks during cycling of the flash memory. In this regard, as flashmemory blocks (e.g., of a solid state drive) are cycled, the datastorage controller may periodically compare (e.g., every 1 k cycles)current program level distributions for wordlines with stored data(e.g., expected values based on predetermined programming levels), andupdate the lookup table with new bias values for a respective memoryblock. For example, if after a certain number of cycles cell leveldistributions for a wordline are not determined to be shifting asanticipated by previous results (or shifting too much), the currentlystored bias values may no longer be appropriate. Accordingly, the datastorage controller may reset the currently stored bias to a defaultvalue (e.g., zero) or adjust the bias value based on the currentlydetermined shift in cell levels. In some aspects, a shift in adistribution of program levels may be determined based on a bit errorrate produced by a read operation.

Current program level distributions for a wordline may be determinedfrom a current error rate for one or more cells associated with thewordline. In this regard, comparing the distributions may includecomparing the current error rate with a stored error rate for thewordline and current memory cycle condition. A delta error raterepresentative of the difference between the current error rate with astored error rate may be determined, and the bias values dynamicallyadjusted based on the delta error rate (or difference). In some aspects,the stored bias values may be modified when the difference satisfies apredetermined threshold (e.g., is greater than a predetermine toleranceof a predetermined value for the current memory cycle condition).Additionally or in the alternative, if the current error rate is greaterthan the stored error rate then the one or more stored bias values maybe increased, while if the current error rate is lower than the storederror rate then the one or more stored bias values may be set to apredetermined value, or reduced.

FIG. 7 depicts an example reduction in a number of errors for cells thathave been subject to wordline compensation, according to one aspect ofthe subject technology. The left side 701 of FIG. 7 depicts a number oferrors for each wordline in an example implementation where nocompensation method has been employed. The right side 702 of FIG. 7depicts a number of errors observed for the same wordline using anexample implementation of the wordline compensation of the subjecttechnology. As depicted by FIG. 7, threshold voltage distribution maychange with both wordline address (number) and program/erase cycle.Accordingly, a default number of errors and a reduced number of errorsfor each wordline can be determined as a result of the characterizationprocess of the subject technology, and used during runtime operations todetermine whether currently stored bias values are effective.

For example, if a higher error rate is determined for a wordline thenthe data storage controller may determine that the error rate is due toa greater than anticipated shift in a corresponding distribution ofprogram levels for the wordline. A bias value for the wordline may thenbe increased or set to a predetermined value for the error rate. On theother hand, if a lower than expected error rate is determined then thedata storage controller may reset the currently stored bias to a defaultvalue. Further improvements to distribution alignment can be obtained byusing different threshold voltage compensation values at differentendurance levels.

FIG. 8 is a block diagram illustrating components of an example datastorage system, according to one aspect of the subject technology. Asdepicted in FIG. 8, in some aspects, data storage system 800 (e.g., asolid state drive) includes data storage controller 801, storage medium802, and flash memory 803. Controller 801 may use storage medium 802 fortemporary storage of data and information used to manage data storagesystem 800. Controller 801 may include several internal components (notshown) such as a read-only memory, a flash component interface (e.g., amultiplexer to manage instruction and data transport along a serialconnection to flash memory 803), an I/O interface, error correctioncircuitry, and the like. In some aspects, all of these elements ofcontroller 801 may be integrated into a single chip. In other aspects,these elements may be separated on their own PC board.

In some implementations, aspects of the subject disclosure may beimplemented in data storage system 800. For example, aspects of thesubject disclosure may be integrated with the function of data storagecontroller 801 or may be implemented as separate components for use inconjunction with data storage controller 801.

Controller 801 may also include a processor that may be configured toexecute code or instructions to perform the operations and functionalitydescribed herein, manage request flow and address mappings, and toperform calculations and generate commands. The processor of controller801 may be configured to monitor and/or control the operation of thecomponents in data storage controller 801. The processor may be ageneral-purpose microprocessor, a microcontroller, a digital signalprocessor (DSP), an application specific integrated circuit (ASIC), afield programmable gate array (FPGA), a programmable logic device (PLD),a controller, a state machine, gated logic, discrete hardwarecomponents, or a combination of the foregoing. One or more sequences ofinstructions may be stored as firmware on ROM within controller 801and/or its processor. One or more sequences of instructions may besoftware stored and read from storage medium 802, flash memory 803, orreceived from host device 804 (e.g., via host interface 805). ROM,storage medium 802, flash memory 803, represent examples of machine orcomputer readable media on which instructions/code executable bycontroller 801 and/or its processor may be stored. Machine or computerreadable media may generally refer to any medium or media used toprovide instructions to controller 801 and/or its processor, includingvolatile media, such as dynamic memory used for storage media 802 or forbuffers within controller 801, and non-volatile media, such aselectronic media, optical media, and magnetic media.

In some aspects, controller 801 may be configured to store data receivedfrom a host device 804 in flash memory 803 in response to a writecommand from host device 804. Controller 801 is further configured toread data stored in flash memory 803 and to transfer the read data tohost device 804 in response to a read command from host device 804. Aswill be described in more detail below, controller 801 is alsoconfigured to predict when current read levels and/or settings aresuspect and to estimate new read levels when it is predicted that thecurrent read levels and/or settings need to be changed. If the estimatedread levels are proven to be insufficient, controller 801 may beconfigured to perform further iterative adjustments to correct the readlevel parameters. By dynamically adjusting read levels of the memory803, the subject technology may extend the number of program/eraseoperations that may be performed on memory cells within flash memory 803in a particular application environment, and increase the endurance ofthe memory cells compared to the same application environment operatingwithout the ability to dynamically adjust read levels.

Host device 804 represents any device configured to be coupled to datastorage system 800 and to store data in data storage system 800. Hostdevice 804 may be a computing system such as a personal computer, aserver, a workstation, a laptop computer, PDA, smart phone, and thelike. Alternatively, host device 804 may be an electronic device such asa digital camera, a digital audio player, a digital video recorder, andthe like.

In some aspects, storage medium 802 represents volatile memory used totemporarily store data and information used to manage data storagesystem 800. According to one aspect of the subject technology, storagemedium 802 is random access memory (RAM) such as double data rate (DDR)RAM. Other types of RAM also may be used to implement storage medium802. Memory 802 may be implemented using a single RAM module or multipleRAM modules. While storage medium 802 is depicted as being distinct fromcontroller 801, those skilled in the art will recognize that storagemedium 802 may be incorporated into controller 801 without departingfrom the scope of the subject technology. Alternatively, storage medium802 may be a non-volatile memory such as a magnetic disk, flash memory,peripheral SSD, and the like.

As further depicted in FIG. 1, data storage system 800 may also includehost interface 805. Host interface 805 may be configured to be operablycoupled (e.g., by wired or wireless connection) to host device 804, toreceive data from host device 804 and to send data to host device 804.Host interface 805 may include electrical and physical connections, or awireless connection, for operably coupling host device 804 to controller801 (e.g., via the I/O interface of controller 801). Host interface 805may be configured to communicate data, addresses, and control signalsbetween host device 804 and controller 801. Alternatively, the I/Ointerface of controller 801 may include and/or be combined with hostinterface 805. Host interface 805 may be configured to implement astandard interface, such as Serial-Attached SCSI (SAS), Fiber Channelinterface, PCI Express (PCIe), SATA, USB, and the like. Host interface805 may be configured to implement only one interface. Alternatively,host interface 805 (and/or the I/O interface of controller 801) may beconfigured to implement multiple interfaces, which may be individuallyselectable using a configuration parameter selected by a user orprogrammed at the time of assembly. Host interface 805 may include oneor more buffers for buffering transmissions between host device 804 andcontroller 801.

Flash memory 803 represents a non-volatile memory device for storingdata. According to one aspect of the subject technology, flash memory803 includes, for example, a NAND flash memory. Flash memory 803 mayinclude a single flash memory device or chip, or, as depicted by FIG. 1,may include multiple flash memory devices or chips arranged in multiplechannels. Flash memory 803 is not limited to any particular capacity orconfiguration. For example, the number of physical blocks, the number ofphysical pages per physical block, the number of sectors per physicalpage, and the size of the sectors may vary within the scope of thesubject technology.

Flash memory may have a standard interface specification so that chipsfrom multiple manufacturers can be used interchangeably (at least to alarge degree). The interface hides the inner working of the flash andreturns only internally detected bit values for data. In one aspect, theinterface of flash memory 803 is used to access one or more internalregisters 806 and an internal flash controller 807 for communication byexternal devices. In some aspects, registers 806 may include address,command, and/or data registers, which internally retrieve and output thenecessary data to and from a NAND memory cell array 808. For example, adata register may include data to be stored in memory array 808, or dataafter a fetch from memory array 808, and may also be used for temporarydata storage and/or act like a buffer. An address register may store thememory address from which data will be fetched to host 804 or theaddress to which data will be sent and stored. In some aspects, acommand register is included to control parity, interrupt control, andthe like. In some aspects, internal flash controller 807 is accessiblevia a control register to control the general behavior of flash memory803. Internal flash controller 807 and/or the control register maycontrol the number of stop bits, word length, receiver clock source, andmay also control switching the addressing mode, paging control,coprocessor control, and the like.

In some aspects, registers 806 may also include a test register. Thetest register may be accessed by specific addresses and/or datacombinations provided at the interface of flash memory 803 (e.g., byspecialized software provided by the manufacturer to perform varioustests on the internal components of the flash memory). In furtheraspects, the test register may be used to access and/or modify otherinternal registers, for example the command and/or control registers. Insome aspects, test modes accessible via the test register may be used toinput or modify certain programming conditions of flash memory 803(e.g., read levels) to dynamically vary how data is read from the memorycells of memory arrays 808.

It should be understood that in all cases data may not always be theresult of a command received from host 804 and/or returned to host 804.In some aspects, Controller 801 may be configured to execute a readoperation independent of host 804 (e.g., to verify read levels or BER).The predicate words “configured to”, “operable to”, and “programmed to”as used herein do not imply any particular tangible or intangiblemodification of a subject, but, rather, are intended to be usedinterchangeably. For example, a processor configured to monitor andcontrol an operation or a component may also mean the processor beingprogrammed to monitor and control the operation or the processor beingoperable to monitor and control the operation. Likewise, a processorconfigured to execute code can be construed as a processor programmed toexecute code or operable to execute code.

Those of skill in the art would appreciate that the various illustrativeblocks, modules, elements, components, methods, and algorithms describedherein may be implemented as electronic hardware, computer software, orcombinations of both. To illustrate this interchangeability of hardwareand software, various illustrative blocks, modules, elements,components, methods, and algorithms have been described above generallyin terms of their functionality. Whether such functionality isimplemented as hardware or software depends upon the particularapplication and design constraints imposed on the overall system.Skilled artisans may implement the described functionality in varyingways for each particular application. Various components and blocks maybe arranged differently (e.g., arranged in a different order, orpartitioned in a different way) all without departing from the scope ofthe subject technology.

It is understood that the specific order or hierarchy of steps in theprocesses disclosed is an illustration of exemplary approaches. Basedupon design preferences, it is understood that the specific order orhierarchy of steps in the processes may be rearranged. Some of the stepsmay be performed simultaneously. The accompanying method claims presentelements of the various steps in a sample order, and are not meant to belimited to the specific order or hierarchy presented.

The previous description is provided to enable any person skilled in theart to practice the various aspects described herein. The previousdescription provides various examples of the subject technology, and thesubject technology is not limited to these examples. Variousmodifications to these aspects will be readily apparent to those skilledin the art, and the generic principles defined herein may be applied toother aspects. Thus, the claims are not intended to be limited to theaspects shown herein, but is to be accorded the full scope consistentwith the language claims, wherein reference to an element in thesingular is not intended to mean “one and only one” unless specificallyso stated, but rather “one or more.” Unless specifically statedotherwise, the term “some” refers to one or more. Pronouns in themasculine (e.g., his) include the feminine and neuter gender (e.g., herand its) and vice versa. Headings and subheadings, if any, are used forconvenience only and do not limit the subject technology.

A phrase such as an “aspect” does not imply that such aspect isessential to the subject technology or that such aspect applies to allconfigurations of the subject technology. A disclosure relating to anaspect may apply to all configurations, or one or more configurations.An aspect may provide one or more examples. A phrase such as an aspectmay refer to one or more aspects and vice versa. A phrase such as an“embodiment” does not imply that such embodiment is essential to thesubject technology or that such embodiment applies to all configurationsof the subject technology. A disclosure relating to an embodiment mayapply to all embodiments, or one or more embodiments. An embodiment mayprovide one or more examples. A phrase such as an “embodiment” may referto one or more embodiments and vice versa. A phrase such as a“configuration” does not imply that such configuration is essential tothe subject technology or that such configuration applies to allconfigurations of the subject technology. A disclosure relating to aconfiguration may apply to all configurations, or one or moreconfigurations. A configuration may provide one or more examples. Aphrase such as a “configuration” may refer to one or more configurationsand vice versa.

The word “exemplary” is used herein to mean “serving as an example orillustration.” Any aspect or design described herein as “exemplary” isnot necessarily to be construed as preferred or advantageous over otheraspects or designs.

All structural and functional equivalents to the elements of the variousaspects described throughout this disclosure that are known or latercome to be known to those of ordinary skill in the art are expresslyincorporated herein by reference and are intended to be encompassed bythe claims. Moreover, nothing disclosed herein is intended to bededicated to the public regardless of whether such disclosure isexplicitly recited in the claims. No claim element is to be construedunder the provisions of 35 U.S.C. §112, sixth paragraph, unless theelement is expressly recited using the phrase “means for” or, in thecase of a method claim, the element is recited using the phrase “stepfor” Furthermore, to the extent that the term “include,” “have,” or thelike is used in the description or the claims, such term is intended tobe inclusive in a manner similar to the term “comprise” as “comprise” isinterpreted when employed as a transitional word in a claim.

What is claimed is:
 1. A method for providing memory cell biasinformation for offsetting operation variations in memory cells,comprising: cycling a plurality of memory cells for one or more cycleintervals; determining, for each cycle interval, a shift in programlevels for the memory cells at one or more memory addresses resultingfrom the cycling; determining, for each cycle interval, one or more biasvalues that when applied to a memory operation causes the memoryoperation to restore the program levels for memory cells at the one ormore memory addresses to within a predetermined tolerance of one or morepredetermined values for the cycle interval and the one or more memoryaddresses, the one or more predetermined values based on predeterminedprogramming data; associating, for each cycle interval, the one or morebias values with the one or more memory addresses; and storing thedetermined bias values and associated memory addresses in a parameterstorage location associated with a memory controller of a solid statestorage device, the parameter storage location configured to beaccessible during storage operations by the memory controller forretrieval of the stored bias values based on a current operation memoryaddress and a current cycle interval.
 2. The method of claim 1, furthercomprising: randomly selecting, before the cycling, the plurality ofmemory cells from a plurality of selected memory die, each dieassociated with a common origin of manufacture.
 3. The method of claim1, wherein the memory addresses associated with the determined biasvalues are wordline addresses.
 4. The method of claim 3, furthercomprising: identifying, for a cycle interval, wordline addressesassociated with bias values within a predetermined deviation of eachother; grouping, for the cycle interval, the wordline addresses into oneor more wordline groups based on the identifying; and associating eachwordline group with a group bias value, the group bias value beingwithin the predetermined deviation of the bias values associated withthe wordlines of the wordline group, wherein the determined bias valuesstored in the parameter storage location comprise the group bias values.5. The method of claim 1, wherein the memory address associations arestored in a lookup table indexed by wordline addresses and cycleintervals.
 6. The method of claim 1, wherein the memory operationcomprises a program verify operation, and wherein each determined biasvalue adjusts a program verify level.
 7. The method of claim 1, whereinthe memory operation comprises a read operation, and wherein eachdetermined bias value adjusts a read level.
 8. The method of claim 1,wherein determining the one or more bias values for a respective cycleinterval comprises: determining that the one or more bias valuesgenerate the lowest bit error rate at the cycle interval for eachrespective memory address compared to other bias values.
 9. The methodof claim 1, wherein each cycle interval comprises a predetermined numberof program/erase cycles.
 10. The method of claim 1, wherein each cycleinterval comprises a predetermined memory retention time.
 11. Anon-transitory machine readable medium having instructions storedthereon that, when executed by a computer-enabled machine, case themachine to perform a method comprising: cycling a plurality of memorycells at one or more memory addresses for one or more cycle intervals;determining, for each cycle interval, a shift in program levels for thememory cells resulting from the cycling; determining, for each cycleinterval, one or more bias values that when applied to a memoryoperation causes the memory operation to restore the program levels formemory cells at the one or more memory addresses to within apredetermined tolerance of one or more predetermined values for thecycle interval and the one or more memory addresses, the one or morepredetermined values based on predetermined programming data;associating, for each cycle interval, the one or more bias values withthe one or more memory addresses; and storing the determined bias valuesand corresponding memory address associations in a parameter storagelocation associated with a memory controller of a solid state storagedevice, the parameter storage location configured to be accessibleduring storage operations by the memory controller for retrieval of thestored bias values based on a current operation memory address and acurrent cycle interval.
 12. The machine readable medium of claim 11,wherein the plurality of memory cells are randomly selected from aplurality of selected memory die, each die associated with a commonorigin of manufacture.
 13. The machine readable medium of claim 11,wherein the memory addresses associated with the determined bias valuesare wordline addresses.
 14. The machine readable medium of claim 13, themethod further comprising: identifying, for a cycle interval, wordlineaddresses associated with bias values within a predetermined deviationof each other; grouping, for the cycle interval, the wordline addressesinto one or more wordline groups based on the identifying; andassociating each wordline group with a group bias value, the group biasvalue being within the predetermined deviation of the bias valuesassociated with the wordlines of the wordline group, wherein thedetermined bias values stored in the parameter storage location comprisethe group bias values.
 15. The machine readable medium of claim 11,wherein the memory address associations are stored in a lookup tableindexed by wordline addresses and cycle intervals.
 16. The machinereadable medium of claim 11, wherein the memory operation comprises aprogram verify operation, and wherein each determined bias value adjustsa program verify level.
 17. The machine readable medium of claim 11,wherein the memory operation comprises a read operation, and whereineach determined bias value adjusts a read level.
 18. The machinereadable medium of claim 11, wherein determining the one or more biasvalues for a respective cycle interval comprises: determining that theone or more bias values generate the lowest bit error rate for eachrespective memory address at the cycle interval compared to other biasvalues.
 19. The machine readable medium of claim 11, wherein each cycleinterval comprises a predetermined number of program/erase cycles. 20.The machine readable medium of claim 11, wherein each cycle intervalcomprises a predetermined memory retention time.